The present invention relates to a method and apparatus for a bias generator. In particular, the present invention relates to a method and apparatus for producing a reference current that is a dependent on a reference clock frequency.
Analog and mixed signal circuits often employ the use of voltage and current reference signals. Typically, such reference signals are DC signals that exhibit insensitivity to certain parameter variations such as power supply variations, processing variations, and temperature variations. One type of reference generator that may be employed is referred to a xe2x80x9cband-gapxe2x80x9d reference circuit.
xe2x80x9cBand-gapxe2x80x9d reference circuits are employed to produce a reference signal that is temperature compensated over a desired temperature range. Bipolar transistors are employed to produce an output voltage that is roughly 1.2V, which corresponds to the band-gap voltage of Silicon. The thermal voltage (Vt) in a bipolar transistor has a positive temperature coefficient (Vt=kT/q), while the base-emitter voltage (Vbe) has a negative temperature coefficient. The band-gap reference circuit is arranged to provide temperature compensation by counteracting the positive temperature variation (Vt) with the negative temperature variation (Vbe) to produce an overall temperature variation that is proportional to (Vbe+nVt), where n is a constant. The constant n is chosen such that the overall temperature coefficient is positive, negative, or approximately zero. The band-gap reference circuit may be utilized to provide a reference signal in an analog (or mixed signal) circuit.
In some instances, analog circuits (or mixed signal circuits) utilize a signal that is not compensated for every parameter, and instead is sensitive to one or more parameters. It may be desirable to produce a reference voltage that increases with increasing temperature. For example, the speed associated with a transistor may degrade as temperature increases. Biasing the quiescent gate potential of the transistor with a voltage that increases with temperature compensates for changes in the speed of the transistor over temperature.
In accordance with the invention, a frequency dependent bias signal is produced for a switched capacitor circuit in response to a reference clock signal. The frequency dependent bias signal is generated by charging and discharging two capacitive circuits in a complimentary out-of-phase manner. The capacitive circuits within the present invention match the type, and orientation of another capacitive circuit that is within the switched capacitor circuit such that parasitic capacitances associated with the capacitive circuits effect the frequency dependant bias signal and the switched capacitor circuit similarly. Ripple in the frequency dependent bias signal is reduced by the complimentary out-of-phase operation, and by an optional ripple filter.
Briefly stated, an electronic circuit generates a bias current that is proportional to a frequency of a reference clock signal in a switched capacitor circuit. The electronic circuit includes a capacitive circuit that is selectively coupled to a transistor that is supplied by a voltage reference circuit. During a first phase, the capacitive circuit is charged by a current from the transistor, and during the second phase, the capacitive circuit is discharged to ground. The duration of each phase is related to the reference clock signal. The average of the current corresponds to a bias signal and is filtered to reduce ripple in the bias signal before the bias signal is received by the switched capacitor circuit. The capacitive circuit is configured with a first and a second capacitor that are arranged in a complimentary out-of-phase configuration. During a first phase, the first capacitor is charged and the second capacitor is discharged. During the second phase, the second capacitor is charged and the first capacitor is discharged. The out-of-phase configuration reduces the size of each of the capacitors used for the capacitive circuit as compared to a single capacitor. The configuration also reduces ripple in the current, which in turn reduces the size of the filter. The frequency dependant current is mirrored into the switched-capacitor circuit. In one example, the electronic circuit is implemented as an integrated circuit including xe2x80x9con-chipxe2x80x9d capacitors that have inherent parasitic capacitances associated therewith. In this instance, the type and orientation of the electronic circuit capacitors should match the switched capacitor circuit capacitors such that parasitic effects track one another.
An embodiment of the invention is directed to an apparatus, producing a frequency dependent bias signal for a switched capacitor circuit, wherein the frequency dependent bias signal is dependent on a reference clock signal that has a corresponding clock frequency, and the switched capacitor circuit includes a type of capacitive circuit. The apparatus includes a control circuit arranged to produce a control signal in response to a reference potential. A controlled circuit is arranged to produce a regulated potential in response to the control signal, wherein the regulated potential is related to the reference potential. A capacitive circuit is included that is the same type as the type of capacitive circuit within the switched capacitor circuit. A discharging circuit is arranged to discharge the capacitive circuit in response to a clock signal when the clock signal corresponds to a first logic level. A charging circuit is arranged to couple a charging current to the capacitive circuit in response to the control signal when the clock signal corresponds to a second logic level that is different from the first logic level such that the charging current charges the capacitive circuit. A sense circuit is arranged to produce the frequency dependent bias signal in response to an average of the charging current, wherein the average of the charging current is related to the clock signal.
Another embodiment of the invention is directed to an apparatus that generates a bias signal that is dependent on a reference clock signal having a corresponding clock frequency and a corresponding pulse-width. The apparatus includes a first capacitive circuit and a second capacitive circuit. A controlled current circuit is arranged to produce a charging current when a sensed potential at a sense node is different from a reference potential. A first charging circuit is arranged to couple the sense node to the first capacitive circuit in response to a first phase of a first clock signal such that the charging current charges the first capacitive circuit to a first charged potential during a first charging phase. A first discharging circuit is arranged to discharge the first capacitive circuit in response to a second phase of the first clock signal. A second charging circuit is arranged to couple the sense node to the second capacitive circuit in response to a first phase of a second clock signal such that the charging current charges the second capacitive circuit to a second charged potential during a second charging phase. A second discharging circuit is arranged to discharge the second capacitive circuit in response to a second phase of the second clock signal. An averaging circuit that is arranged to produce the bias signal in response to an average charging current, wherein the average charging current corresponds to an average of the charging current that is produced by the controlled current circuit such that the bias signal changes with changes in the reference clock signal.
Yet another embodiment of the invention is directed to a method for generating a frequency dependent bias signal. The method includes: sensing a potential at a sense node to produce a sensed potential, coupling a charging current to the sense node when the sensed potential is different from a reference potential, coupling the sense node to a first capacitive circuit such that the first capacitive circuit charges with a first charging current during a first phase of a first clock signal, decoupling the sense node from the first capacitive circuit during a second phase of the first clock signal, discharging the first capacitive circuit during the second phase of the first clock signal, coupling the sense node to a second capacitive circuit such that the second capacitive circuit charges with a second charging current during a first phase of a second clock signal, wherein the first phase of the first clock signal is inactive when the first phase of the second clock signal is active, decoupling the sense node from the second capacitive circuit during a second phase of the second clock signal, discharging the second capacitive circuit during the second phase of the second clock signal, and generating a bias signal in response to an average current that corresponds to an average of the first and second charging currents such that the bias signal is related to a frequency associated with the first and second clock signals.
Yet another embodiment of the invention is directed to an apparatus, providing a bias signal for a switched-capacitor circuit that uses a reference clock signal with a corresponding reference clock frequency. The apparatus includes a means for producing a first clock signal arranged to produce a first clock signal in response to the reference clock signal, the first clock signal having a first and second phase. A means for producing a second clock signal is arranged to produce a second clock signal in response to the reference clock signal, the second clock signal having a first and second phase, wherein the first phase of the second clock signal is non-overlapping with respect to the first phase of the first clock signal. A means for sensing is arranged to sense a sensed potential at a sense node. A means for producing a current is arranged to provide a charging current when the sensed potential is different from a reference potential. A first means for charging is arranged to couple the sense node to a first capacitive circuit such that the first capacitive circuit is charged with a first charging current to a first charged potential in response to the first phase of the first clock signal. A first means for discharging is arranged to discharge the first capacitive circuit in response to the second phase of the first clock signal. A second means for charging is arranged to couple the sense node to a second capacitive circuit such that the second capacitive circuit is charged with a second charging current to a second charged potential in response to the first phase of the second clock signal. A second means for discharging is arranged to discharge the second capacitive circuit in response to the second phase of the second clock signal. An averaging means is arranged to produce the bias signal in response to an average of the charging current, wherein the average of the charging current corresponds to the first and second charging currents such that the average of the charging current is related to the reference clock frequency.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detail description of presently preferred embodiments of the invention, and to the appended claims.